In the semiconductor fabrication industry, it is necessary to test an integrated circuit during fabrication by pre-testing and after fabrication by final testing, in order to obtain better detection of any defects occurring therein. However, as the degree of integration and complexity of integrated circuits continues to increase, the number of external connections available has not kept pace so that it has become more and more difficult to test complex integrated circuits.
Complicating testing of BiCMOS ICs is the need to isolate BiCMOS logic from the bipolar circuits during certain testing processes. Also, multiple bipolar circuit pathways may be coupled between supply voltage V.sub.DD and an intermediate supply voltage V.sub.TT, wherein V.sub.DD &gt;V.sub.TT &gt;GND. (Typically, today's BiCMOS devices operate with a 3.6 volts V.sub.DD supply voltage and a 1.5 volts V.sub.TT supply voltage.) Further, because of a limitation on the number of connections available, a BiCMOS integrated circuit may have CMOS logic coupled in parallel with certain bipolar circuits between an operating circuit voltage V.sub.DD and a ground potential. These bipolar circuits (such as ECL I/O circuits) commonly have a high standby current.
One well known circuit test in the semiconductor fabrication art is the "IDD test" or "IDD current test". This test attempts to measure the quiescent current of a chip between supply voltage V.sub.DD and ground potential GND. The test is conventionally used to screen early AC,DC and reliability defects in CMOS and BiCMOS logic parts. Industry standards are well established for IDD current test measurements and various articles are available in the open literature which describe the testing process. Essentially the test seeks to determine the extent of leakage current through the BiCMOS logic. The amount of leakage current is recognized as an indication of the quality of a chip. The lower the magnitude of the leakage current, the better the chip quality.
In the BiCMOS environment, the IDD test is traditionally conducted on a per cycle/per pattern basis on internal logic circuits with separate power busing for the bipolar circuits, i.e., separate voltage rails are employed to separately supply voltage V.sub.DD to the logic and to the bipolar circuits. Because separate power supply rails are used, leakage current through the logic circuits is obviously isolated from standby current through the bipolar circuits, which is normally at least an order of magnitude higher than the leakage current. In this configuration, isolation is ensured by removing the supply voltage V.sub.DD at the voltage rail supplying the bipolar circuits. Unfortunately, in view of ever increasing integrated circuit complexity, many BiCMOS circuit designs must utilize a common pin for supplying voltage V.sub.DD to the bipolar circuit pathways and to the internal logic.
Again, bipolar circuit bias current is typically much higher than leakage current in the BiCMOS logic portion of a semiconductor chip. (For example, in BiCMOS logic designs, IDD current is typically on the order of microamps while bipolar circuit bias current is in the range of milliamps.) In the common power supply rail embodiment, the high currents drawn by the I/O related bipolar circuits make it difficult during IDD testing to detect the low level quiescent IDD currents of the BiCMOS logic coupled in parallel therewith. Therefore, a recognized need exists in such circuits to isolate the bipolar circuit pathways from the parallel coupled BiCMOS logic pathways for accurate testing thereof.
One prior attempt to address this problem is described in Japanese Patent No. 63-186462 entitled "Semiconductor Integrated Circuit". In this patent, a BiCMOS integrated circuit is presented which allows measurement of only the power source current of a CMOS circuit by providing a switching circuit to cut off the power source current of the bipolar circuit portion at the time of the test processing. A MOSFET switching circuit is described which is responsive to an applied signal at a dedicated test terminal. By applying an appropriate voltage at the test terminal, switching of the bipolar circuit can be obtained, i.e., power source current can be made to flow only in the CMOS circuit portion of the BiCMOS IC. The disadvantage to the approach, however, remains the need to dedicate an additional terminal (i.e., the test terminal) to attain the desired isolation of the CMOS logic.
Therefore, a need exists in the industry for a means for shutting off IDD current through bipolar circuits coupled in parallel with BiCMOS logic between supply voltage V.sub.DD and ground potential GND. Such selective isolation would allow meaningful IDD testing in a BiCMOS environment without the addition of an extra terminal to accomplish the test.